1. Field of the Invention
The present invention generally relates to bus architectures. More particularly, the present invention relates to the use of serialization tokens by devices coupled to a bus.
2. Background Information
Many types of electrical systems include at least one “bus” over which electrical components may communicate with one another in a coordinated manner. By way of example, such components may include processors, memory modules, etc. Some integrated circuits, such as processors, may internally include a processor core and one or more memory devices coupled together via a bus.
Some types of busses permit a bus “master” to be coupled to one or more slaves. In such architectures, the master may be responsible for initiating transactions on the bus that target the slaves. The transactions initiated by the master may include “write” transactions in which data is provided to a slave, “read” transactions in which data is provided by a slave to the master, and other types of transactions. In some architectures, transactions processed by the slaves preferably are processed in the same order that the transactions are issued by the master. Accordingly, a mechanism for accomplishing the correct ordering is needed in such architectures. It is also generally desirable to minimize the amount of latency on the bus, thereby increasing the effective bandwidth of the bus.